mirror of https://github.com/YosysHQ/yosys.git
27 lines
433 B
Plaintext
27 lines
433 B
Plaintext
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read_verilog <<EOT
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module top(input a, output [1:0] b);
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wire c;
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(* submod="bar" *) sub s1(a, c);
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assign b[0] = c;
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endmodule
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module sub(input a, output c);
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assign c = a;
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endmodule
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EOT
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hierarchy -top top
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proc
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design -save gold
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submod
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flatten
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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