mirror of https://github.com/YosysHQ/yosys.git
33 lines
797 B
Systemverilog
33 lines
797 B
Systemverilog
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module functions01;
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wire [5:2]x;
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wire [3:0]y[2:7];
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wire [3:0]z[7:2][2:9];
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//wire [$size(x)-1:0]x_size;
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//wire [$size({x, x})-1:0]xx_size;
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//wire [$size(y)-1:0]y_size;
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//wire [$size(z)-1:0]z_size;
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assert property ($size(x) == 4);
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assert property ($size({3{x}}) == 3*4);
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assert property ($size(y) == 6);
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assert property ($size(y, 1) == 6);
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assert property ($size(y, (1+1)) == 4);
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assert property ($size(z) == 6);
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assert property ($size(z, 1) == 6);
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assert property ($size(z, 2) == 8);
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assert property ($size(z, 3) == 4);
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// This should trigger an error if enabled (it does).
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//assert property ($size(z, 4) == 4);
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//wire [$bits(x)-1:0]x_bits;
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//wire [$bits({x, x})-1:0]xx_bits;
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assert property ($bits(x) == 4);
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assert property ($bits(y) == 4*6);
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assert property ($bits(z) == 4*6*8);
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endmodule
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