yosys/techlibs/ice40/brams.txt

bram $__ICE40_RAM4K_M0
  init 1
  abits 8
  dbits 16
  groups 2
  ports  1  1
  wrmode 0  1
  enable 1 16
  transp 0  0
  clocks 2  3
  clkpol 2  3
endbram

bram $__ICE40_RAM4K_M123
  init 1
  abits  9 @M1
  dbits  8 @M1
  abits 10 @M2
  dbits  4 @M2
  abits 11 @M3
  dbits  2 @M3
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 1
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

match $__ICE40_RAM4K_M0
  min efficiency 2
  make_transp
  or_next_if_better
endmatch

match $__ICE40_RAM4K_M123
  min efficiency 2
  make_transp
endmatch
Added ice40 bram support 2015-04-23 17:06:50 -05:00			`bram $__ICE40_RAM4K_M0`
initialized iCE40 brams (mode 0) 2015-04-25 13:44:51 -05:00			`init 1`
Added ice40 bram support 2015-04-23 17:06:50 -05:00			`abits 8`
			`dbits 16`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 16`
Added ice40 bram support 2015-04-23 17:06:50 -05:00			`transp 0 0`
			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

			`bram $__ICE40_RAM4K_M123`
Initialization support for all iCE40 bram modes 2015-04-26 01:39:31 -05:00			`init 1`
Added ice40 bram support 2015-04-23 17:06:50 -05:00			`abits 9 @M1`
			`dbits 8 @M1`
			`abits 10 @M2`
			`dbits 4 @M2`
			`abits 11 @M3`
			`dbits 2 @M3`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 1`
Added ice40 bram support 2015-04-23 17:06:50 -05:00			`transp 0 0`
			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

			`match $__ICE40_RAM4K_M0`
iCE40: set min bram efficiency to 2% 2015-06-20 02:31:19 -05:00			`min efficiency 2`
Added ice40 bram support 2015-04-23 17:06:50 -05:00			`make_transp`
			`or_next_if_better`
			`endmatch`

			`match $__ICE40_RAM4K_M123`
iCE40: set min bram efficiency to 2% 2015-06-20 02:31:19 -05:00			`min efficiency 2`
Added ice40 bram support 2015-04-23 17:06:50 -05:00			`make_transp`
			`endmatch`