mirror of https://github.com/YosysHQ/yosys.git
19 lines
516 B
Plaintext
19 lines
516 B
Plaintext
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read_verilog dpram.v
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hierarchy -top top
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proc
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memory -nomap
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equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#Blocked by issue #1358 (Missing ECP5 simulation models)
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#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
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#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd top
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select -assert-count 1 t:DP16KD
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select -assert-none t:DP16KD %% t:* %D
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