mirror of https://github.com/YosysHQ/yosys.git
59 lines
1.7 KiB
Plaintext
59 lines
1.7 KiB
Plaintext
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# Verify xilinx cell models
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read_verilog xl_cells.v
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read_verilog xl_cells_tb.v
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rename GND MY_GND
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rename INV MY_INV
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rename LUT2 MY_LUT2
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rename LUT3 MY_LUT3
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rename LUT4 MY_LUT4
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rename LUT5 MY_LUT5
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rename LUT6 MY_LUT6
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rename MUXCY MY_MUXCY
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rename MUXF7 MY_MUXF7
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rename VCC MY_VCC
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rename XORCY MY_XORCY
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read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/GND.v
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read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/INV.v
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# read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/LUT2.v
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# read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/LUT3.v
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# read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/LUT4.v
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# read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/LUT5.v
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# read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/LUT6.v
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read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/MUXCY.v
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read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/MUXF7.v
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read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/VCC.v
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read_verilog /opt/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims/XORCY.v
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rename GND XL_GND
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rename INV XL_INV
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# rename LUT2 XL_LUT2
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# rename LUT3 XL_LUT3
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# rename LUT4 XL_LUT4
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# rename LUT5 XL_LUT5
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# rename LUT6 XL_LUT6
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rename MUXCY XL_MUXCY
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rename MUXF7 XL_MUXF7
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rename VCC XL_VCC
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rename XORCY XL_XORCY
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proc
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flatten
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opt_clean
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sat -verify -prove ok 1'b1 TB_GND
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sat -verify -prove ok 1'b1 TB_INV
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# sat -verify -prove ok 1'b1 TB_LUT2
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# sat -verify -prove ok 1'b1 TB_LUT3
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# sat -verify -prove ok 1'b1 TB_LUT4
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# sat -verify -prove ok 1'b1 TB_LUT5
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# sat -verify -prove ok 1'b1 TB_LUT6
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sat -verify -prove ok 1'b1 TB_MUXCY
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sat -verify -prove ok 1'b1 TB_MUXF7
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sat -verify -prove ok 1'b1 TB_VCC
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sat -verify -prove ok 1'b1 TB_XORCY
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