2019-10-18 05:19:59 -05:00
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read_verilog ../common/counter.v
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2019-09-10 00:08:03 -05:00
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hierarchy -top top
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proc
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flatten
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2019-10-17 10:24:53 -05:00
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equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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2019-09-10 00:08:03 -05:00
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDCE
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2019-11-24 07:17:46 -06:00
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select -assert-count 1 t:INV
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2019-09-10 00:08:03 -05:00
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select -assert-count 7 t:MUXCY
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select -assert-count 8 t:XORCY
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2019-12-28 09:12:45 -06:00
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select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
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