mirror of https://github.com/YosysHQ/yosys.git
77 lines
1.7 KiB
Verilog
77 lines
1.7 KiB
Verilog
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// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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module BRAM_TDP #(parameter AWIDTH = 10,
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parameter DWIDTH = 36)(
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clk_a,
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rce_a,
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ra_a,
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rq_a,
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wce_a,
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wa_a,
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wd_a,
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clk_b,
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rce_b,
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ra_b,
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rq_b,
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wce_b,
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wa_b,
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wd_b
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);
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input clk_a;
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input rce_a;
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input [AWIDTH-1:0] ra_a;
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output reg [DWIDTH-1:0] rq_a;
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input wce_a;
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input [AWIDTH-1:0] wa_a;
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input [DWIDTH-1:0] wd_a;
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input clk_b;
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input rce_b;
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input [AWIDTH-1:0] ra_b;
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output reg [DWIDTH-1:0] rq_b;
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input wce_b;
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input [AWIDTH-1:0] wa_b;
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input [DWIDTH-1:0] wd_b;
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(* no_rw_check = 1 *)
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reg [DWIDTH-1:0] memory[0:(1<<AWIDTH)-1];
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wire [AWIDTH-1:0] a_a = rce_a ? ra_a : wa_a;
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wire [AWIDTH-1:0] a_b = rce_b ? ra_b : wa_b;
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wire ce_a = rce_a || wce_a;
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wire ce_b = rce_b || wce_b;
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always @(posedge clk_a) begin
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if (ce_a) begin
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if (wce_a)
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memory[a_a] <= wd_a;
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rq_a <= memory[a_a];
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end
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end
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always @(posedge clk_b) begin
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if (ce_b) begin
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if (wce_b)
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memory[a_b] <= wd_b;
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rq_b <= memory[a_b];
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end
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end
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endmodule
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