mirror of https://github.com/YosysHQ/yosys.git
42 lines
862 B
Bash
42 lines
862 B
Bash
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#!/bin/bash
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set -ex
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XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
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../../yosys - <<- EOT
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# read design
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read_verilog counter.v
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# high-level synthesis
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hierarchy -check -top counter
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proc; opt; fsm; opt; techmap; opt
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# mapping logic to LUTs using Berkeley ABC
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abc -lut 6; opt
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# map internal cells to FPGA cells
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techmap -map cells.v; opt
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# write netlist
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write_verilog -noattr testbench_synth.v
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EOT
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iverilog -o testbench_gold counter_tb.v counter.v
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iverilog -o testbench_gate counter_tb.v testbench_synth.v \
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$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
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./testbench_gold > testbench_gold.txt
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./testbench_gate > testbench_gate.txt
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if diff -u testbench_gold.txt testbench_gate.txt; then
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set +x; echo; echo; banner " PASS "
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else
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exit 1
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fi
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if [ "$*" = "-clean" ]; then
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rm -f testbench_{synth.v,{gold,gate}{,.txt}}
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fi
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