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21 lines
439 B
Verilog
21 lines
439 B
Verilog
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// Copied from techlibs/common/simlib.v
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// with this condition removed: (^{P, G, CI} !== 1'bx)
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module lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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input [WIDTH-1:0] P; // Propagate
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input [WIDTH-1:0] G; // Generate
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input CI; // Carry-in
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output reg [WIDTH-1:0] CO; // Carry-out
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integer i;
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always @* begin
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CO[0] = G[0] || (P[0] && CI);
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for (i = 1; i < WIDTH; i = i+1)
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CO[i] = G[i] || (P[i] && CO[i-1]);
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end
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endmodule
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