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techmap: add TCL test for Han-Carlson adder
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yosys -import
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read_verilog +/choices/han-carlson.v
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read_verilog lcu_refined.v
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design -save init
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for {set i 1} {$i <= 16} {incr i} {
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design -load init
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chparam -set WIDTH $i
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yosys proc
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equiv_make -blacklist han-carlson.nomatch lcu _85_lcu_han_carlson equiv
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equiv_simple equiv
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equiv_status -assert equiv
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}
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// Copied from techlibs/common/simlib.v
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// with this condition removed: (^{P, G, CI} !== 1'bx)
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module lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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input [WIDTH-1:0] P; // Propagate
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input [WIDTH-1:0] G; // Generate
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input CI; // Carry-in
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output reg [WIDTH-1:0] CO; // Carry-out
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integer i;
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always @* begin
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CO[0] = G[0] || (P[0] && CI);
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for (i = 1; i < WIDTH; i = i+1)
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CO[i] = G[i] || (P[i] && CO[i-1]);
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end
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endmodule
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#!/usr/bin/env bash
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set -eu
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source ../gen-tests-makefile.sh
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run_tests --yosys-scripts --bash --yosys-args "-e 'select out of bounds'"
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run_tests --yosys-scripts --tcl-scripts --bash --yosys-args "-e 'select out of bounds'"
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