mirror of https://github.com/YosysHQ/yosys.git
42 lines
781 B
Plaintext
42 lines
781 B
Plaintext
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read_verilog << EOT
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module sub (input i, output o);
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parameter _TECHMAP_CELLNAME_ = "";
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namedsub #(.name(_TECHMAP_CELLNAME_)) _TECHMAP_REPLACE_ (i, o);
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endmodule
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EOT
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design -stash map
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read_verilog << EOT
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(* blackbox *)
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module sub (input i, output o);
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endmodule
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(* blackbox *)
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module namedsub (input i, output o);
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parameter name = "";
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endmodule
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module top(input [3:0] i, output [3:0] o);
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sub s1 (i[0], o[0]);
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sub subsubsub (i[1], o[1]);
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sub s2 (i[2], o[2]);
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sub xxx (i[3], o[3]);
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endmodule
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EOT
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techmap -map %map
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select -assert-count 4 t:namedsub
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select -assert-count 0 t:sub
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select -assert-count 1 t:namedsub r:name=s1 %i
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select -assert-count 1 t:namedsub r:name=subsubsub %i
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select -assert-count 1 t:namedsub r:name=s2 %i
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select -assert-count 1 t:namedsub r:name=xxx %i
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