yosys/tests/sim/sim_dffsr.ys

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2022-02-15 02:35:53 -06:00
read_verilog dffsr.v
proc
opt_dff
stat
select -assert-count 1 t:$dffsr
sim -clock clk -r tb_dffsr.fst -scope tb_dffsr.uut -sim-cmp dffsr