yosys/tests/anlogic/tribuf.ys

read_verilog tribuf.v
hierarchy -top tristate
proc
flatten
equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`read_verilog tribuf.v`
Cleanup top modules and not used defines 2019-10-04 03:57:47 -05:00			`hierarchy -top tristate`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`proc`
			`flatten`
			`equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check`
			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
Cleanup top modules and not used defines 2019-10-04 03:57:47 -05:00			`cd tristate # Constrain all select calls below inside the top module`
Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. 2019-09-23 04:12:02 -05:00			`select -assert-count 1 t:$_TBUF_`
			`select -assert-none t:$_TBUF_ %% t:* %D`