riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,739 Commits 112 Branches 50 Tags 53 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
Miodrag Milanovic 3d3479b0af Cleanup top modules and not used defines 2019-10-04 10:57:47 +02:00
SergeyDegtyar 27377c4663 Add new tests for Anlogic architecture 
Problems/questions:
	- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
		Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
	- Internal cell type $_TBUF_  is present.
 2019-09-23 12:12:02 +03:00