mirror of https://github.com/YosysHQ/yosys.git
212 lines
7.2 KiB
Coq
212 lines
7.2 KiB
Coq
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
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assign Y = A;
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endmodule
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module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
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assign Y = A;
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endmodule
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module \$__ABC9_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
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parameter WIDTH = 1;
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assign O = I;
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endmodule
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(* techmap_celltype = "$__ABC9_DSP48E1_MULT_P_MUX $__ABC9_DSP48E1_MULT_PCOUT_MUX $__ABC9_DSP48E1_MULT_DPORT_P_MUX $__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC9_DSP48E1_P_MUX $__ABC9_DSP48E1_PCOUT_MUX" *)
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module \$__ABC9_DSP48E1_MUX (
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input Aq, Bq, Cq, Dq, ADq,
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input [47:0] I,
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input Mq,
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input [47:0] P,
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input Pq,
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output [47:0] O
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);
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assign O = I;
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endmodule
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(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *)
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module \$__ABC9_DSP48E1 (
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(* techmap_autopurge *) output [29:0] ACOUT,
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(* techmap_autopurge *) output [17:0] BCOUT,
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(* techmap_autopurge *) output reg CARRYCASCOUT,
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(* techmap_autopurge *) output reg [3:0] CARRYOUT,
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(* techmap_autopurge *) output reg MULTSIGNOUT,
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(* techmap_autopurge *) output OVERFLOW,
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(* techmap_autopurge *) output reg signed [47:0] P,
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(* techmap_autopurge *) output PATTERNBDETECT,
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(* techmap_autopurge *) output PATTERNDETECT,
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(* techmap_autopurge *) output [47:0] PCOUT,
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(* techmap_autopurge *) output UNDERFLOW,
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(* techmap_autopurge *) input signed [29:0] A,
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(* techmap_autopurge *) input [29:0] ACIN,
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(* techmap_autopurge *) input [3:0] ALUMODE,
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(* techmap_autopurge *) input signed [17:0] B,
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(* techmap_autopurge *) input [17:0] BCIN,
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(* techmap_autopurge *) input [47:0] C,
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(* techmap_autopurge *) input CARRYCASCIN,
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(* techmap_autopurge *) input CARRYIN,
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(* techmap_autopurge *) input [2:0] CARRYINSEL,
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(* techmap_autopurge *) input CEA1,
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(* techmap_autopurge *) input CEA2,
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(* techmap_autopurge *) input CEAD,
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(* techmap_autopurge *) input CEALUMODE,
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(* techmap_autopurge *) input CEB1,
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(* techmap_autopurge *) input CEB2,
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(* techmap_autopurge *) input CEC,
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(* techmap_autopurge *) input CECARRYIN,
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(* techmap_autopurge *) input CECTRL,
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(* techmap_autopurge *) input CED,
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(* techmap_autopurge *) input CEINMODE,
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(* techmap_autopurge *) input CEM,
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(* techmap_autopurge *) input CEP,
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(* techmap_autopurge *) input CLK,
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(* techmap_autopurge *) input [24:0] D,
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(* techmap_autopurge *) input [4:0] INMODE,
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(* techmap_autopurge *) input MULTSIGNIN,
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(* techmap_autopurge *) input [6:0] OPMODE,
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(* techmap_autopurge *) input [47:0] PCIN,
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(* techmap_autopurge *) input RSTA,
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(* techmap_autopurge *) input RSTALLCARRYIN,
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(* techmap_autopurge *) input RSTALUMODE,
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(* techmap_autopurge *) input RSTB,
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(* techmap_autopurge *) input RSTC,
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(* techmap_autopurge *) input RSTCTRL,
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(* techmap_autopurge *) input RSTD,
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(* techmap_autopurge *) input RSTINMODE,
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(* techmap_autopurge *) input RSTM,
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(* techmap_autopurge *) input RSTP
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);
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parameter integer ACASCREG = 1;
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parameter integer ADREG = 1;
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parameter integer ALUMODEREG = 1;
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parameter integer AREG = 1;
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parameter AUTORESET_PATDET = "NO_RESET";
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parameter A_INPUT = "DIRECT";
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parameter integer BCASCREG = 1;
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parameter integer BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter integer CARRYINREG = 1;
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parameter integer CARRYINSELREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer INMODEREG = 1;
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parameter integer MREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter SEL_MASK = "MASK";
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parameter SEL_PATTERN = "PATTERN";
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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parameter USE_PATTERN_DETECT = "NO_PATDET";
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parameter USE_SIMD = "ONE48";
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parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
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parameter [47:0] PATTERN = 48'h000000000000;
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parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
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parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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parameter [4:0] IS_INMODE_INVERTED = 5'b0;
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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DSP48E1 #(
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.ACASCREG(ACASCREG),
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.ADREG(ADREG),
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.ALUMODEREG(ALUMODEREG),
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.AREG(AREG),
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.AUTORESET_PATDET(AUTORESET_PATDET),
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.A_INPUT(A_INPUT),
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.BCASCREG(BCASCREG),
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.BREG(BREG),
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.B_INPUT(B_INPUT),
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.CARRYINREG(CARRYINREG),
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.CARRYINSELREG(CARRYINSELREG),
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.CREG(CREG),
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.DREG(DREG),
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.INMODEREG(INMODEREG),
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.MREG(MREG),
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.OPMODEREG(OPMODEREG),
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.PREG(PREG),
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.SEL_MASK(SEL_MASK),
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.SEL_PATTERN(SEL_PATTERN),
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.USE_DPORT(USE_DPORT),
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.USE_MULT(USE_MULT),
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.USE_PATTERN_DETECT(USE_PATTERN_DETECT),
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.USE_SIMD(USE_SIMD),
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.MASK(MASK),
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.PATTERN(PATTERN),
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.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
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.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
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.IS_CLK_INVERTED(IS_CLK_INVERTED),
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.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
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.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
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) _TECHMAP_REPLACE_ (
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.ACOUT(ACOUT),
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.BCOUT(BCOUT),
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.CARRYCASCOUT(CARRYCASCOUT),
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.CARRYOUT(CARRYOUT),
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.MULTSIGNOUT(MULTSIGNOUT),
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.OVERFLOW(OVERFLOW),
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.P(P),
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.PATTERNBDETECT(PATTERNBDETECT),
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.PATTERNDETECT(PATTERNDETECT),
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.PCOUT(PCOUT),
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.UNDERFLOW(UNDERFLOW),
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.A(A),
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.ACIN(ACIN),
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.ALUMODE(ALUMODE),
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.B(B),
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.BCIN(BCIN),
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.C(C),
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.CARRYCASCIN(CARRYCASCIN),
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.CARRYIN(CARRYIN),
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.CARRYINSEL(CARRYINSEL),
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.CEA1(CEA1),
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.CEA2(CEA2),
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.CEAD(CEAD),
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.CEALUMODE(CEALUMODE),
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.CEB1(CEB1),
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.CEB2(CEB2),
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.CEC(CEC),
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.CECARRYIN(CECARRYIN),
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.CECTRL(CECTRL),
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.CED(CED),
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.CEINMODE(CEINMODE),
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.CEM(CEM),
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.CEP(CEP),
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.CLK(CLK),
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.D(D),
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.INMODE(INMODE),
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.MULTSIGNIN(MULTSIGNIN),
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.OPMODE(OPMODE),
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.PCIN(PCIN),
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.RSTA(RSTA),
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.RSTALLCARRYIN(RSTALLCARRYIN),
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.RSTALUMODE(RSTALUMODE),
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.RSTB(RSTB),
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.RSTC(RSTC),
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.RSTCTRL(RSTCTRL),
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.RSTD(RSTD),
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.RSTINMODE(RSTINMODE),
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.RSTM(RSTM),
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.RSTP(RSTP)
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);
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endmodule
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