2018-12-01 11:28:54 -06:00
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OBJS += techlibs/anlogic/synth_anlogic.o
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OBJS += techlibs/anlogic/anlogic_eqn.o
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2019-08-12 13:19:54 -05:00
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OBJS += techlibs/anlogic/anlogic_fixcarry.o
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2018-12-01 11:28:54 -06:00
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
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2018-12-18 20:23:58 -06:00
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
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Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 06:30:00 -06:00
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v))
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2021-12-17 06:25:32 -06:00
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams.txt))
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$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/brams_map.v))
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