mirror of https://github.com/YosysHQ/yosys.git
22 lines
342 B
Verilog
22 lines
342 B
Verilog
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module \$pmux (A, B, S, Y);
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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parameter WIDTH = 1;
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parameter S_WIDTH = 1;
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input [WIDTH-1:0] A;
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input [WIDTH*S_WIDTH-1:0] B;
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input [S_WIDTH-1:0] S;
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output reg [WIDTH-1:0] Y;
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integer i;
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always @* begin
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Y <= A;
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for (i = 0; i < S_WIDTH; i=i+1)
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if (S[i]) Y <= B[WIDTH*i +: WIDTH];
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end
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endmodule
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