mirror of https://github.com/YosysHQ/yosys.git
20 lines
258 B
Plaintext
20 lines
258 B
Plaintext
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read_verilog <<EOT
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module top(inout io);
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wire in;
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wire t;
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wire o;
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IOBUF IOBUF(
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.I(in),
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.T(t),
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.IO(io),
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.O(o)
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);
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endmodule
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EOT
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synth_xilinx
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cd top
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select -assert-count 1 t:IOBUF
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select -assert-none t:* t:IOBUF %d
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