mirror of https://github.com/YosysHQ/yosys.git
25 lines
285 B
Plaintext
25 lines
285 B
Plaintext
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read_verilog <<EOT
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module t (...);
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input CLK;
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input [10:0] A;
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input WE;
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input C;
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input [7:0] DI;
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output reg [7:0] DO;
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reg [7:0] mem[2047:0];
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always @(posedge CLK) begin
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if (C)
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if (WE)
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mem[A] <= DI;
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DO <= mem[A];
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end
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endmodule
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EOT
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synth_ecp5
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select -assert-count 1 t:DP16KD
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