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12 lines
277 B
Plaintext
12 lines
277 B
Plaintext
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read_verilog <<EOT
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module top(input [15:0] a, b, output [31:0] o1, o2, o5);
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SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1));
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assign o2 = a * 16'd0;
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wire [31:0] o3, o4;
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SB_MAC16 m2 (.A(a), .B(b), .O(o3));
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assign o4 = a * b;
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SB_MAC16 m3 (.A(a), .B(b), .O(o5));
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endmodule
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EOT
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ice40_dsp
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