mirror of https://github.com/YosysHQ/yosys.git
35 lines
435 B
Plaintext
35 lines
435 B
Plaintext
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read_verilog -sv <<EOT
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module Task_Test_Top
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(
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input a,
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output b
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);
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task SomeTaskName(a);
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b = ~a;
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endtask
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always @*
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SomeTaskName(a);
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assert property (b == ~a);
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endmodule
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EOT
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proc
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sat -verify -prove-asserts
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design -reset
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logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
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read_verilog -sv <<EOT
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module Task_Test_Top
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(
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);
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task SomeTaskName(a)
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endtask
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endmodule
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EOT
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