2019-10-18 05:19:59 -05:00
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read_verilog ../common/counter.v
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2019-08-30 01:45:33 -05:00
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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2019-08-30 04:38:28 -05:00
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select -assert-count 6 t:SB_CARRY
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2019-08-30 01:45:33 -05:00
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select -assert-count 8 t:SB_DFFR
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select -assert-count 8 t:SB_LUT4
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select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D
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