mirror of https://github.com/YosysHQ/yosys.git
25 lines
1.7 KiB
Plaintext
25 lines
1.7 KiB
Plaintext
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# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
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code_hdl_models_arbiter.v error: reg rst; cannot be driven by primitives or continuous assignment.
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code_hdl_models_clk_div_45.v yosys issue: 2nd PMUXTREE pass yields: ERROR: Negative edge clock on FF clk_div_45.$procdff$49.
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code_hdl_models_d_ff_gates.v combinational loop
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code_hdl_models_d_latch_gates.v combinational loop
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code_hdl_models_dff_async_reset.v $adff
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code_hdl_models_tff_async_reset.v $adff
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code_hdl_models_uart.v $adff
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code_specman_switch_fabric.v subfield assignment (bits() <= ...)
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code_tidbits_asyn_reset.v $adff
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code_tidbits_reg_seq_example.v $adff
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code_verilog_tutorial_always_example.v empty module
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code_verilog_tutorial_escape_id.v make_id issues (name begins with a digit)
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code_verilog_tutorial_explicit.v firrtl backend bug (empty module)
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code_verilog_tutorial_first_counter.v error: reg rst; cannot be driven by primitives or continuous assignment.
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code_verilog_tutorial_fsm_full.v error: reg reset; cannot be driven by primitives or continuous assignment.
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code_verilog_tutorial_if_else.v empty module (everything is under 'always @ (posedge clk)')
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[code_verilog_tutorial_n_out_primitive.v empty module
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code_verilog_tutorial_parallel_if.v empty module (everything is under 'always @ (posedge clk)')
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code_verilog_tutorial_simple_function.v empty module (no hardware)
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code_verilog_tutorial_simple_if.v empty module (everything is under 'always @ (posedge clk)')
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code_verilog_tutorial_task_global.v empty module (everything is under 'always @ (posedge clk)')
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code_verilog_tutorial_v2k_reg.v empty module
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code_verilog_tutorial_which_clock.v $adff
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