yosys/backends/btor/btor.ys

proc; 
opt; opt_const -mux_undef; splice; opt;
rename -hide;;;
#converting pmux to mux
techmap -share_map pmux2mux.v;;
memory_dff -wr_only; memory_collect;;
#flatten design
flatten;;
#converting asyn memory write to syn memory
memory_unpack; 
#cell output to be a single wire
splitnets -driver;
setundef -zero -undriven;
opt;;;
btor 2014-01-03 03:52:44 -06:00			`proc;`
added concat and slice cell translation 2014-02-11 06:06:01 -06:00			`opt; opt_const -mux_undef; splice; opt;`
BTOR backend 2014-01-14 05:03:53 -06:00			`rename -hide;;;`
btor 2014-01-03 03:52:44 -06:00			`#converting pmux to mux`
Use techmap -share_map in btor scripts 2014-01-24 08:52:16 -06:00			`techmap -share_map pmux2mux.v;;`
added concat and slice cell translation 2014-02-11 06:06:01 -06:00			`memory_dff -wr_only; memory_collect;;`
btor 2014-01-03 03:52:44 -06:00			`#flatten design`
verilog default options pull shift operator width issues 2014-01-17 12:32:35 -06:00			`flatten;;`
			`#converting asyn memory write to syn memory`
			`memory_unpack;`
BTOR backend 2014-01-14 05:03:53 -06:00			`#cell output to be a single wire`
			`splitnets -driver;`
script added 2014-01-18 14:54:52 -06:00			`setundef -zero -undriven;`
BTOR backend 2014-01-14 05:03:53 -06:00			`opt;;;`
script added 2014-01-18 14:54:52 -06:00