2019-10-18 05:19:59 -05:00
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read_verilog ../common/counter.v
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2019-09-23 04:12:02 -05:00
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 9 t:AL_MAP_ADDER
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select -assert-count 8 t:AL_MAP_SEQ
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2019-10-04 04:09:59 -05:00
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select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D
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