mirror of https://github.com/YosysHQ/yosys.git
66 lines
1.4 KiB
Verilog
66 lines
1.4 KiB
Verilog
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`default_nettype none
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`ifdef ARITH_ha
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(* techmap_celltype = "$alu" *)
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module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y, CO;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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wire [Y_WIDTH:0] CARRY;
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LUT4_HA #(
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.INIT(16'b0),
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.I0MUX(1'b1)
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) carry_statrt (
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.I0(), .I1(CI), .I2(CI), .I3(),
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.Ci(),
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.Co(CARRY[0])
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);
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// Carry chain
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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LUT4_HA #(
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.INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0)
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.I0MUX(1'b1)
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) lut_i (
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.I0(), .I1(AA[i]), .I2(BB[i]), .I3(),
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.Ci(CARRY[i]),
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.O(Y[i]),
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.Co(CARRY[i+1])
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);
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assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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`endif
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