2019-10-28 09:18:01 -05:00
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read_verilog ../common/tribuf.v
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hierarchy -top tristate
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proc
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tribuf
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flatten
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synth
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equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd tristate # Constrain all select calls below inside the top module
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#Internal cell type used. Need support it.
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select -assert-count 1 t:TBUF
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2021-08-20 14:21:06 -05:00
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select -assert-count 1 t:LUT1
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2019-10-28 09:18:01 -05:00
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select -assert-count 2 t:IBUF
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2021-08-20 14:21:06 -05:00
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select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
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