yosys/tests/arch/efinix/tribuf.ys

read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
flatten
synth
equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
#Internal cell type used. Need support it.
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D
Share common tests 2019-10-18 05:19:59 -05:00			`read_verilog ../common/tribuf.v`
Cleaned tests 2019-10-04 05:42:06 -05:00			`hierarchy -top tristate`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`proc`
			`tribuf`
			`flatten`
			`synth`
			`equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check`
			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
Cleaned tests 2019-10-04 05:42:06 -05:00			`cd tristate # Constrain all select calls below inside the top module`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`#Internal cell type used. Need support it.`
			`select -assert-count 1 t:$_TBUF_`
			`select -assert-none t:$_TBUF_ %% t:* %D`