2013-01-05 04:13:26 -06:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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2015-07-02 04:14:30 -05:00
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*
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2013-01-05 04:13:26 -06:00
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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2019-07-02 07:27:37 -05:00
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#include <algorithm>
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2015-06-14 09:15:51 -05:00
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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2013-01-05 04:13:26 -06:00
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2014-09-27 09:17:53 -05:00
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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2015-06-14 09:15:51 -05:00
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struct MemoryDffWorker
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2013-01-05 04:13:26 -06:00
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{
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2015-06-14 09:15:51 -05:00
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Module *module;
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SigMap sigmap;
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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vector<Cell*> dff_cells;
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dict<SigBit, SigBit> invbits;
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dict<SigBit, int> sigbit_users_count;
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2015-09-25 05:23:11 -05:00
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dict<SigSpec, Cell*> mux_cells_a, mux_cells_b;
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2015-10-31 16:01:41 -05:00
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pool<Cell*> forward_merged_dffs, candidate_dffs;
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2018-05-28 10:16:15 -05:00
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pool<SigBit> init_bits;
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2015-06-14 09:15:51 -05:00
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2018-05-28 10:16:15 -05:00
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MemoryDffWorker(Module *module) : module(module), sigmap(module)
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{
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for (auto wire : module->wires()) {
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if (wire->attributes.count("\\init") == 0)
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continue;
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SigSpec sig = sigmap(wire);
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2018-12-18 11:40:01 -06:00
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Const initval = wire->attributes.at("\\init");
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2018-05-28 10:16:15 -05:00
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for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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init_bits.insert(sig[i]);
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}
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}
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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bool find_sig_before_dff(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
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2013-01-05 04:13:26 -06:00
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{
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2015-06-14 09:15:51 -05:00
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sigmap.apply(sig);
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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for (auto &bit : sig)
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2013-01-05 04:13:26 -06:00
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{
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2015-06-14 09:15:51 -05:00
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if (bit.wire == NULL)
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continue;
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2015-06-09 00:19:04 -05:00
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2018-05-28 10:16:15 -05:00
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if (!after && init_bits.count(sigmap(bit)))
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return false;
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2015-06-14 09:15:51 -05:00
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for (auto cell : dff_cells)
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{
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2015-10-31 16:01:41 -05:00
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if (after && forward_merged_dffs.count(cell))
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continue;
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2015-06-14 09:15:51 -05:00
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SigSpec this_clk = cell->getPort("\\CLK");
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bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
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2015-06-09 00:19:04 -05:00
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2015-06-14 09:15:51 -05:00
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if (invbits.count(this_clk)) {
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this_clk = invbits.at(this_clk);
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this_clk_polarity = !this_clk_polarity;
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}
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
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if (this_clk != clk)
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continue;
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if (this_clk_polarity != clk_polarity)
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continue;
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}
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
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sigmap.apply(q_norm);
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
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if (d.size() != 1)
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continue;
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2018-05-28 10:16:15 -05:00
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if (after && init_bits.count(d))
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return false;
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2015-06-14 09:15:51 -05:00
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bit = d;
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clk = this_clk;
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clk_polarity = this_clk_polarity;
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2015-10-31 16:01:41 -05:00
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candidate_dffs.insert(cell);
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2015-06-14 09:15:51 -05:00
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goto replaced_this_bit;
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}
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return false;
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replaced_this_bit:;
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2013-01-05 04:13:26 -06:00
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}
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2015-06-14 09:15:51 -05:00
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return true;
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2013-01-05 04:13:26 -06:00
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}
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2015-06-14 09:15:51 -05:00
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void handle_wr_cell(RTLIL::Cell *cell)
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{
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log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
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bool clk_polarity = 0;
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2015-10-31 16:01:41 -05:00
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candidate_dffs.clear();
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
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if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
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log("no (compatible) $dff for address input found.\n");
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return;
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}
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
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if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
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log("no (compatible) $dff for data input found.\n");
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return;
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}
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec sig_en = cell->getPort("\\EN");
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if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
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log("no (compatible) $dff for enable input found.\n");
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return;
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}
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2013-01-05 04:13:26 -06:00
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2015-10-31 16:01:41 -05:00
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if (clk != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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for (auto cell : candidate_dffs)
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forward_merged_dffs.insert(cell);
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2015-06-14 09:15:51 -05:00
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cell->setPort("\\CLK", clk);
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cell->setPort("\\ADDR", sig_addr);
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cell->setPort("\\DATA", sig_data);
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cell->setPort("\\EN", sig_en);
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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2015-10-31 16:01:41 -05:00
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2015-06-14 09:15:51 -05:00
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log("merged $dff to cell.\n");
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return;
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}
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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log("no (compatible) $dff found.\n");
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2013-12-01 07:08:18 -06:00
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}
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2014-06-01 04:32:27 -05:00
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2015-06-14 09:15:51 -05:00
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void disconnect_dff(RTLIL::SigSpec sig)
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{
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sigmap.apply(sig);
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sig.sort_and_unify();
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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std::stringstream sstr;
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sstr << "$memory_dff_disconnected$" << (autoidx++);
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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for (auto cell : module->cells())
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if (cell->type == "$dff") {
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RTLIL::SigSpec new_q = cell->getPort("\\Q");
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new_q.replace(sig, new_sig);
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cell->setPort("\\Q", new_q);
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}
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}
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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void handle_rd_cell(RTLIL::Cell *cell)
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{
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log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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bool clk_polarity = 0;
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
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2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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for (auto bit : sigmap(sig_data))
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if (sigbit_users_count[bit] > 1)
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goto skip_ff_after_read_merging;
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2013-01-05 04:13:26 -06:00
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2015-09-25 05:23:11 -05:00
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if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
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2015-06-14 09:15:51 -05:00
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{
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2019-06-24 20:33:06 -05:00
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RTLIL::SigSpec en;
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2019-07-02 07:27:37 -05:00
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std::vector<RTLIL::SigSpec> check_q;
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2015-09-25 05:23:11 -05:00
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2019-06-24 20:33:06 -05:00
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do {
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bool enable_invert = mux_cells_a.count(sig_data) != 0;
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Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
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2019-07-02 07:27:37 -05:00
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check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
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2019-06-24 20:33:06 -05:00
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sig_data = sigmap(mux->getPort("\\Y"));
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en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
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} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
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2015-09-25 05:23:11 -05:00
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2019-06-25 10:33:17 -05:00
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for (auto bit : sig_data)
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if (sigbit_users_count[bit] > 1)
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goto skip_ff_after_read_merging;
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2019-06-25 10:29:55 -05:00
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2019-07-02 07:27:37 -05:00
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if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) &&
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std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
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2015-09-25 05:23:11 -05:00
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{
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disconnect_dff(sig_data);
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cell->setPort("\\CLK", clk_data);
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2019-06-24 20:33:06 -05:00
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cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
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2015-09-25 05:23:11 -05:00
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cell->setPort("\\DATA", sig_data);
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
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log("merged data $dff with rd enable to cell.\n");
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return;
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}
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}
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else
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{
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if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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disconnect_dff(sig_data);
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cell->setPort("\\CLK", clk_data);
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cell->setPort("\\EN", State::S1);
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cell->setPort("\\DATA", sig_data);
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
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log("merged data $dff to cell.\n");
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return;
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}
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2015-06-14 09:15:51 -05:00
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}
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2014-02-03 06:01:45 -06:00
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2015-06-14 09:15:51 -05:00
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skip_ff_after_read_merging:;
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RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
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RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
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if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
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clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
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{
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cell->setPort("\\CLK", clk_addr);
|
2015-09-25 05:23:11 -05:00
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cell->setPort("\\EN", State::S1);
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2015-06-14 09:15:51 -05:00
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cell->setPort("\\ADDR", sig_addr);
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cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
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cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
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log("merged address $dff to cell.\n");
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return;
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}
|
2013-01-05 04:13:26 -06:00
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2015-06-14 09:15:51 -05:00
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log("no (compatible) $dff found.\n");
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}
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2014-08-06 07:31:38 -05:00
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2015-06-14 09:15:51 -05:00
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void run(bool flag_wr_only)
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{
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for (auto wire : module->wires()) {
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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sigbit_users_count[bit]++;
|
2015-06-09 00:19:04 -05:00
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}
|
2014-08-06 07:31:38 -05:00
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2015-06-14 09:15:51 -05:00
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for (auto cell : module->cells()) {
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if (cell->type == "$dff")
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dff_cells.push_back(cell);
|
2015-09-25 05:23:11 -05:00
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if (cell->type == "$mux") {
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mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
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mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
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}
|
2019-08-06 18:18:18 -05:00
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if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
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2015-06-14 09:15:51 -05:00
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SigSpec sig_a = cell->getPort("\\A");
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SigSpec sig_y = cell->getPort("\\Y");
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if (cell->type == "$not")
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|
|
sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
|
|
|
|
if (cell->type == "$logic_not")
|
|
|
|
sig_y.extend_u0(1);
|
|
|
|
for (int i = 0; i < GetSize(sig_y); i++)
|
|
|
|
invbits[sig_y[i]] = sig_a[i];
|
|
|
|
}
|
|
|
|
for (auto &conn : cell->connections())
|
|
|
|
if (!cell->known() || cell->input(conn.first))
|
|
|
|
for (auto bit : sigmap(conn.second))
|
|
|
|
sigbit_users_count[bit]++;
|
|
|
|
}
|
2014-09-16 05:40:58 -05:00
|
|
|
|
|
|
|
for (auto cell : module->selected_cells())
|
2015-06-14 09:15:51 -05:00
|
|
|
if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
|
|
|
|
handle_wr_cell(cell);
|
|
|
|
|
|
|
|
if (!flag_wr_only)
|
|
|
|
for (auto cell : module->selected_cells())
|
|
|
|
if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
|
|
|
|
handle_rd_cell(cell);
|
|
|
|
}
|
|
|
|
};
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
struct MemoryDffPass : public Pass {
|
2013-03-01 03:17:35 -06:00
|
|
|
MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
|
2018-07-21 01:41:18 -05:00
|
|
|
void help() YS_OVERRIDE
|
2013-03-01 03:17:35 -06:00
|
|
|
{
|
|
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
|
|
log("\n");
|
2014-02-03 06:01:45 -06:00
|
|
|
log(" memory_dff [options] [selection]\n");
|
2013-03-01 03:17:35 -06:00
|
|
|
log("\n");
|
|
|
|
log("This pass detects DFFs at memory ports and merges them into the memory port.\n");
|
|
|
|
log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
|
|
|
|
log("interface and yields a synchronous memory port.\n");
|
|
|
|
log("\n");
|
2015-06-14 09:15:51 -05:00
|
|
|
log(" -nordfff\n");
|
2014-02-03 06:01:45 -06:00
|
|
|
log(" do not merge registers on read ports\n");
|
|
|
|
log("\n");
|
2013-03-01 03:17:35 -06:00
|
|
|
}
|
2018-07-21 01:41:18 -05:00
|
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
2014-02-03 06:01:45 -06:00
|
|
|
{
|
|
|
|
bool flag_wr_only = false;
|
|
|
|
|
2016-04-21 16:28:37 -05:00
|
|
|
log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
|
2014-02-03 06:01:45 -06:00
|
|
|
|
|
|
|
size_t argidx;
|
|
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
2015-06-14 09:15:51 -05:00
|
|
|
if (args[argidx] == "-nordff" || args[argidx] == "-wr_only") {
|
2014-02-03 06:01:45 -06:00
|
|
|
flag_wr_only = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
extra_args(args, argidx, design);
|
|
|
|
|
2015-06-14 09:15:51 -05:00
|
|
|
for (auto mod : design->selected_modules()) {
|
|
|
|
MemoryDffWorker worker(mod);
|
|
|
|
worker.run(flag_wr_only);
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
} MemoryDffPass;
|
2015-07-02 04:14:30 -05:00
|
|
|
|
2014-09-27 09:17:53 -05:00
|
|
|
PRIVATE_NAMESPACE_END
|