This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
0b1b94d85e
yosys
/
examples
/
anlogic
/
demo.ys
4 lines
65 B
Plaintext
Raw
Normal View
History
Unescape
Escape
Added examples/anlogic/
2019-03-04 11:56:56 -06:00
read_verilog demo.v
synth_anlogic -top demo
examples/anlogic/ now also output the SVF file.
2019-03-05 22:21:11 -06:00
write_verilog full.v