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examples/anlogic/ now also output the SVF file.

This commit is contained in:
Kali Prasad 2019-03-06 09:51:11 +05:30
parent d03780c3f4
commit 7c03b0b082
6 changed files with 12 additions and 10 deletions
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5
examples/anlogic/.gitignore vendored
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@ -1,4 +1,7 @@
demo.bit
demo_phy.area
full.v
*.log
*.log
*.h
*.tde
*.svf

1
examples/anlogic/README
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@ -10,4 +10,3 @@ set TD_HOME env variable to the full path to the TD <TD Install Directory> as fo
export TD_HOME=<TD Install Directory>
then run "bash build.sh" in this directory.

2
examples/anlogic/build.tcl
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@ -8,4 +8,4 @@ pack
place
route
report_area -io_info -file demo_phy.area
bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000
bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000

2
examples/anlogic/demo.adc
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@ -1,2 +1,2 @@
set_pin_assignment {CLK_IN} { LOCATION = K14; } ##24MHZ
set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED
set_pin_assignment {R_LED} { LOCATION = R3; } ##R_LED

10
examples/anlogic/demo.v
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@ -1,18 +1,18 @@
module demo (
input wire CLK_IN,
output wire R_LED
input wire CLK_IN,
output wire R_LED
);
parameter time1 = 30'd12_000_000;
reg led_state;
reg [29:0] count;
always @(posedge CLK_IN)begin
if(count == time1)begin
count<= 30'd0;
count<= 30'd0;
led_state <= ~led_state;
end
else
count <= count + 1'b1;
end
assign R_LED = led_state;
endmodule
endmodule

2
examples/anlogic/demo.ys
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@ -1,3 +1,3 @@
read_verilog demo.v
synth_anlogic -top demo
write_verilog full.v
write_verilog full.v