mirror of https://github.com/YosysHQ/yosys.git
28 lines
512 B
Verilog
28 lines
512 B
Verilog
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// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-rd-clk \clk
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// expect-rd-en \re
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// expect-rd-arst-sig \reset
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// expect-rd-arst-val 8'01011010
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// expect-rd-init-val 8'00111100
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module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
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reg [7:0] bram[0:255];
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initial rdata = 8'h3c;
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always @(posedge clk) begin
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if (we)
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bram[addr] <= wdata;
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end
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always @(posedge clk, posedge reset) begin
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if (reset)
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rdata <= 8'h5a;
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else if (re)
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rdata <= bram[addr];
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end
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endmodule
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