yosys/backends/intersynth/intersynth.cc

/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *  
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *  
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/rtlil.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
#include <string>
#include <assert.h>


static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
{
	sig.optimize();

	if (sig.chunks.size() != 1)
error:
		log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));

	conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width));

	if (sig.chunks[0].wire == NULL) {
		celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.width, sig.width, sig.width));
		constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.width, sig.chunks[0].data.as_int(),
				sig.width, sig.width, sig.chunks[0].data.as_int(), sig.chunks[0].data.as_int()));
		return stringf("CONST_%d_0x%x", sig.width, sig.chunks[0].data.as_int());
	}

	if (sig.chunks[0].offset != 0 || sig.width != sig.chunks[0].wire->width)
		goto error;

	return RTLIL::unescape_id(sig.chunks[0].wire->name);
}

struct IntersynthBackend : public Backend {
	IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
	virtual void help()
	{
		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
		log("\n");
		log("    write_intersynth [options] [filename]\n");
		log("\n");
		log("Write the current design to an 'intersynth' netlist file. InterSynth is\n");
		log("a tool for Coarse-Grain Example-Driven Interconnect Synthesis.\n");
		log("\n");
		log("    -notypes\n");
		log("        do not generate celltypes and conntypes commands. i.e. just output\n");
		log("        the netlists. this is used for postsilicon synthesis.\n");
		log("\n");
		log("    -lib <verilog_or_ilang_file>\n");
		log("        Use the specified library file for determining whether cell ports are\n");
		log("        inputs or outputs. This option can be used multiple times to specify\n");
		log("        more than one library.\n");
		log("\n");
		log("    -selected\n");
		log("        only write selected modules. modules must be selected entirely or\n");
		log("        not at all.\n");
		log("\n");
		log("http://www.clifford.at/intersynth/\n");
		log("\n");
	}
	virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
	{
		log_header("Executing INTERSYNTH backend.\n");
		log_push();

		std::vector<std::string> libfiles;
		std::vector<RTLIL::Design*> libs;
		bool flag_notypes = false;
		bool selected = false;

		size_t argidx;
		for (argidx = 1; argidx < args.size(); argidx++)
		{
			if (args[argidx] == "-notypes") {
				flag_notypes = true;
				continue;
			}
			if (args[argidx] == "-lib" && argidx+1 < args.size()) {
				libfiles.push_back(args[++argidx]);
				continue;
			}
			if (args[argidx] == "-selected") {
				selected = true;
				continue;
			}
			break;
		}
		extra_args(f, filename, args, argidx);

		log("Output filename: %s\n", filename.c_str());

		for (auto filename : libfiles) {
			FILE *f = fopen(filename.c_str(), "rt");
			if (f == NULL)
				log_error("Can't open lib file `%s'.\n", filename.c_str());
			RTLIL::Design *lib = new RTLIL::Design;
			Frontend::frontend_call(lib, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
			libs.push_back(lib);
			fclose(f);
		}

		if (libs.size() > 0)
			log_header("Continuing INTERSYNTH backend.\n");

		std::set<std::string> conntypes_code, celltypes_code;
		std::string netlists_code;
		CellTypes ct(design);

		for (auto lib : libs)
			ct.setup_design(lib);

		for (auto module_it : design->modules)
		{
			RTLIL::Module *module = module_it.second;
			SigMap sigmap(module);

			if (module->get_bool_attribute("\\blackbox"))
				continue;
			if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
				continue;

			if (selected && !design->selected_whole_module(module->name)) {
				if (design->selected_module(module->name))
					log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(module->name));
				continue;
			}

			log("Generating netlist %s.\n", RTLIL::id2cstr(module->name));

			if (module->memories.size() != 0 || module->processes.size() != 0)
				log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");

			std::set<std::string> constcells_code;
			netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));

			for (auto wire_it : module->wires) {
				RTLIL::Wire *wire = wire_it.second;
				if (wire->port_input || wire->port_output) {
					celltypes_code.insert(stringf("celltype !%s b%d %sPORT\n" "%s %s %d %s PORT\n",
							RTLIL::id2cstr(wire->name), wire->width, wire->port_input ? "*" : "",
							wire->port_input ? "input" : "output", RTLIL::id2cstr(wire->name), wire->width, RTLIL::id2cstr(wire->name)));
					netlists_code += stringf("node %s %s PORT %s\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(wire->name),
							netname(conntypes_code, celltypes_code, constcells_code, sigmap(wire)).c_str());
				}
			}

			for (auto cell_it : module->cells)
			{
				RTLIL::Cell *cell = cell_it.second;
				std::string celltype_code, node_code;

				if (!ct.cell_known(cell->type))
					log_error("Found unknown cell type %s in module!\n", RTLIL::id2cstr(cell->type));

				celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type));
				node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
				for (auto &port : cell->connections) {
					RTLIL::SigSpec sig = sigmap(port.second);
					if (sig.width != 0) {
						conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width));
						celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
						node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
					}
				}
				for (auto &param : cell->parameters) {
					celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first));
					if (param.second.bits.size() != 32) {
						node_code += stringf(" %s '", RTLIL::id2cstr(param.first));
						for (int i = param.second.bits.size()-1; i >= 0; i--)
							node_code += param.second.bits[i] == RTLIL::S1 ? "1" : "0";
					} else
						node_code += stringf(" %s 0x%x", RTLIL::id2cstr(param.first), param.second.as_int());
				}

				celltypes_code.insert(celltype_code + "\n");
				netlists_code += node_code + "\n";
			}

			for (auto code : constcells_code)
				netlists_code += code;
		}

		if (!flag_notypes) {
			for (auto code : conntypes_code)
				fprintf(f, "%s", code.c_str());
			for (auto code : celltypes_code)
				fprintf(f, "%s", code.c_str());
		}
		fprintf(f, "%s", netlists_code.c_str());

		for (auto lib : libs)
			delete lib;

		log_pop();
	}
} IntersynthBackend;