yosys/manual/PRESENTATION_Intro/counter.ys

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# read design
read_verilog counter.v
hierarchy -check -top counter
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show -notitle -stretch -format pdf -prefix counter_00
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# the high-level stuff
proc; opt; memory; opt; fsm; opt
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show -notitle -stretch -format pdf -prefix counter_01
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# mapping to internal cell library
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techmap; opt
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splitnets -ports;;
show -notitle -stretch -format pdf -prefix counter_02
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# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
# mapping logic to mycells.lib
abc -liberty mycells.lib
# cleanup
clean
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show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03