mirror of https://github.com/YosysHQ/yosys.git
26 lines
383 B
Plaintext
26 lines
383 B
Plaintext
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read_ilang << EOF
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module \top
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wire width 4 input 1 \A
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wire output 2 \O
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cell \LUT4 $0
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parameter \INIT 16'1111110011000000
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connect \I0 \A [0]
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connect \I1 \A [1]
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connect \I2 \A [2]
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connect \I3 \A [3]
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connect \O \O
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end
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end
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EOF
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equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
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design -load postopt
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select -assert-count 1 t:LUT3
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