mirror of https://github.com/YosysHQ/yosys.git
15 lines
277 B
Plaintext
15 lines
277 B
Plaintext
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logger -expect log ".*cells_not_processed=[01]* .*" 1
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logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
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read_verilog <<EOT
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module mux2(a, b, s, y);
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input a, b, s;
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output y;
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wire s_n = ~s;
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wire t0 = s & a;
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wire t1 = s_n & b;
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assign y = t0 | t1;
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endmodule
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EOT
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printattrs
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