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18 lines
253 B
Plaintext
18 lines
253 B
Plaintext
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read_verilog <<EOT
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module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
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reg [2:0] aa, bb;
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always @(posedge clk) begin
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if (ce) begin
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aa <= a;
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end
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bb <= b;
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q <= aa + bb;
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end
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endmodule
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EOT
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synth_ice40 -abc9 -dffe_min_ce_use 4
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