mirror of https://github.com/YosysHQ/yosys.git
8 lines
198 B
Plaintext
8 lines
198 B
Plaintext
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read_verilog -icells <<EOT
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module top(input clk, d, output q);
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\$_DFF_N_ dffn(.C(clk), .D(d), .Q(q));
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endmodule
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EOT
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write_aiger -zinit -ywmap aiger_dff.out /dev/null
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!grep -qF negedge aiger_dff.out
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