mirror of https://github.com/YosysHQ/yosys.git
9 lines
128 B
Verilog
9 lines
128 B
Verilog
|
module adlatch( input d, rst, en, output reg q );
|
||
|
|
always @* begin
|
||
|
|
if (rst)
|
||
|
|
q = 0;
|
||
|
|
else if (en)
|
||
|
|
q = d;
|
||
|
|
end
|
||
|
|
endmodule
|