mirror of https://github.com/YosysHQ/yosys.git
14 lines
206 B
Verilog
14 lines
206 B
Verilog
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module tb;
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reg clk = 1'b0;
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reg [31:0] data;
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m dut(.clk(clk), .data(data));
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initial begin
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data = 32'haa;
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#10; clk = 1; #10; clk = 0;
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data = 32'haaaa;
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#10; clk = 1; #10; clk = 0;
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end
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endmodule
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