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14 lines
203 B
Plaintext
14 lines
203 B
Plaintext
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read_verilog <<EOT
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module t(input [3:0] A, input [3:0] B, input [3:0] C, input S, output [3:0] Y);
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wire [3:0] t = A + C;
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assign Y = S ? A + B : {4{t[0]}};
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endmodule
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EOT
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equiv_opt -assert opt_share
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