mirror of https://github.com/YosysHQ/yosys.git
18 lines
274 B
Verilog
18 lines
274 B
Verilog
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module m(input clk, rst, en, input [31:0] data);
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`ifdef EVENT_CLK
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always @(posedge clk)
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`endif
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`ifdef EVENT_CLK_RST
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always @(posedge clk or negedge rst)
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`endif
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`ifdef EVENT_STAR
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always @(*)
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`endif
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`ifdef COND_EN
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if (en)
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`endif
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$display("data=%d", data);
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endmodule
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