2023-08-11 20:59:39 -05:00
|
|
|
#!/usr/bin/env bash
|
2019-02-04 18:46:24 -06:00
|
|
|
|
2019-06-07 13:05:36 -05:00
|
|
|
set -e
|
2019-06-07 13:28:05 -05:00
|
|
|
|
2019-06-27 21:54:09 -05:00
|
|
|
OPTIND=1
|
|
|
|
abcprog="../../yosys-abc" # default to built-in version of abc
|
|
|
|
while getopts "A:" opt
|
|
|
|
do
|
|
|
|
case "$opt" in
|
|
|
|
A) abcprog="$OPTARG" ;;
|
|
|
|
esac
|
|
|
|
done
|
|
|
|
shift "$((OPTIND-1))"
|
|
|
|
|
2019-06-10 12:27:55 -05:00
|
|
|
# NB: *.aag and *.aig must contain a symbol table naming the primary
|
|
|
|
# inputs and outputs, otherwise ABC and Yosys will name them
|
|
|
|
# arbitrarily (and inconsistently with each other).
|
|
|
|
|
2019-06-07 13:28:05 -05:00
|
|
|
for aag in *.aag; do
|
|
|
|
# Since ABC cannot read *.aag, read the *.aig instead
|
2019-06-10 12:27:55 -05:00
|
|
|
# (which would have been created by the reference aig2aig utility,
|
|
|
|
# available from http://fmv.jku.at/aiger/)
|
2019-06-19 05:20:35 -05:00
|
|
|
echo "Checking $aag."
|
2019-06-27 21:54:09 -05:00
|
|
|
$abcprog -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
|
2019-06-19 05:20:35 -05:00
|
|
|
../../yosys -qp "
|
2019-06-07 13:28:05 -05:00
|
|
|
read_verilog ${aag%.*}_ref.v
|
|
|
|
prep
|
|
|
|
design -stash gold
|
|
|
|
read_aiger -clk_name clock $aag
|
|
|
|
prep
|
|
|
|
design -stash gate
|
|
|
|
design -import gold -as gold
|
|
|
|
design -import gate -as gate
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
|
|
sat -verify -prove-asserts -show-ports -seq 16 miter
|
2020-01-07 13:44:03 -06:00
|
|
|
" -l ${aag}.log
|
2019-06-07 13:28:05 -05:00
|
|
|
done
|
|
|
|
|
2019-06-07 13:05:36 -05:00
|
|
|
for aig in *.aig; do
|
2019-06-19 05:20:35 -05:00
|
|
|
echo "Checking $aig."
|
2019-06-27 21:54:09 -05:00
|
|
|
$abcprog -q "read -c $aig; write ${aig%.*}_ref.v"
|
2019-06-19 05:20:35 -05:00
|
|
|
../../yosys -qp "
|
2019-06-07 13:05:36 -05:00
|
|
|
read_verilog ${aig%.*}_ref.v
|
|
|
|
prep
|
|
|
|
design -stash gold
|
|
|
|
read_aiger -clk_name clock $aig
|
|
|
|
prep
|
|
|
|
design -stash gate
|
|
|
|
design -import gold -as gold
|
|
|
|
design -import gate -as gate
|
|
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
|
|
sat -verify -prove-asserts -show-ports -seq 16 miter
|
2020-01-07 13:44:03 -06:00
|
|
|
" -l ${aig}.log
|
2019-02-04 18:46:24 -06:00
|
|
|
done
|
2020-05-02 11:56:10 -05:00
|
|
|
|
|
|
|
for y in *.ys; do
|
|
|
|
echo "Running $y."
|
2020-09-23 05:48:26 -05:00
|
|
|
../../yosys -ql ${y%.*}.log $y
|
2020-05-02 11:56:10 -05:00
|
|
|
done
|