mirror of https://github.com/YosysHQ/yosys.git
91 lines
2.5 KiB
Verilog
91 lines
2.5 KiB
Verilog
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$alu" *)
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module _80_ccu2d_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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function integer round_up2;
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input integer N;
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begin
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round_up2 = ((N + 1) / 2) * 2;
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end
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endfunction
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localparam Y_WIDTH2 = round_up2(Y_WIDTH);
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(* force_downto *)
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wire [Y_WIDTH2-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BX = B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH2-1:0] FCO, Y1;
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genvar i;
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generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
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CCU2D #(
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.INIT0(16'b0101_1010_1001_0110),
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.INIT1(16'b0101_1010_1001_0110),
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.INJECT1_0("NO"),
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.INJECT1_1("NO")
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) ccu2d_i (
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.CIN(C[i]),
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.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b0),
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.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b0),
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.S0(Y[i]), .S1(Y1[i]),
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.COUT(FCO[i])
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);
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assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
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if (i+1 < Y_WIDTH) begin
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assign CO[i+1] = FCO[i];
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assign Y[i+1] = Y1[i];
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end
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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