mirror of https://github.com/YosysHQ/yosys.git
11 lines
149 B
Verilog
11 lines
149 B
Verilog
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module test(input A, B, C, D, E,
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output reg Y);
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always @* begin
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Y <= A;
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if (B)
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Y <= C;
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if (D)
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Y <= E;
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end
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endmodule
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