2020-07-14 17:58:07 -05:00
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### Always-active EN removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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2022-08-25 07:24:31 -05:00
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output [11:0] Q;
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2020-07-14 17:58:07 -05:00
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input SRST;
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input ARST;
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input [1:0] CLR;
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input [1:0] SET;
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .EN(1'b1), .D(D), .Q(Q[1:0]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .EN(1'b0), .ARST(ARST), .D(D), .Q(Q[3:2]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .EN(1'b1), .SRST(SRST), .D(D), .Q(Q[5:4]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(1'b1), .SRST(SRST), .D(D), .Q(Q[7:6]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff4 (.CLK(CLK), .EN(1'b0), .SET(SET), .CLR(CLR), .D(D), .Q(Q[9:8]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff5 (.EN(1'b1), .D(D), .Q(Q[11:10]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff6 (.EN(1'b0), .ARST(ARST), .D(D), .Q(Q[13:12]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.EN(1'b0), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
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endmodule
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EOT
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design -save orig
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# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
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delete top/ff6 top/ff7
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equiv_opt -undef -assert -multiclock opt_dff
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design -load orig
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delete top/ff6 top/ff7
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load orig
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opt_dff
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select -assert-count 0 t:$dffe
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select -assert-count 0 t:$adffe
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select -assert-count 0 t:$sdffe
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select -assert-count 0 t:$sdffce
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select -assert-count 0 t:$dffsre
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$adlatch
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select -assert-count 0 t:$dlatchsr
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select -assert-count 1 t:$dff
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select -assert-count 2 t:$sdff
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$dffsr
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design -load orig
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simplemap
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opt_dff
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select -assert-count 0 t:$_DFFE_*
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select -assert-count 0 t:$_SDFFE_*
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select -assert-count 0 t:$_SDFFCE_*
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select -assert-count 0 t:$_DFFSRE_*
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select -assert-count 0 t:$_DLATCH*
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select -assert-count 2 t:$_DFF_P_
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select -assert-count 4 t:$_SDFF_PP?_
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select -assert-count 2 t:$_DFF_PP?_
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select -assert-count 2 t:$_DFFSR_PNP_
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design -reset
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### Never-active EN removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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(* init = 32'h55555555 *)
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output [31:0] Q;
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input SRST;
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input ARST;
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input [1:0] CLR;
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input [1:0] SET;
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff0 (.CLK(CLK), .EN(1'b0), .D(D), .Q(Q[1:0]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .EN(1'b1), .ARST(ARST), .D(D), .Q(Q[3:2]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .EN(1'b0), .SRST(SRST), .D(D), .Q(Q[5:4]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .EN(1'b0), .SRST(SRST), .D(D), .Q(Q[7:6]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff4 (.CLK(CLK), .EN(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[9:8]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff5 (.EN(1'b0), .D(D), .Q(Q[11:10]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff6 (.EN(1'b1), .ARST(ARST), .D(D), .Q(Q[13:12]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.EN(1'b1), .SET(SET), .CLR(CLR), .D(D), .Q(Q[15:14]));
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(2)) ff8 (.CLK(CLK), .EN(1'bx), .D(D), .Q(Q[17:16]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff9 (.CLK(CLK), .EN(1'bx), .ARST(ARST), .D(D), .Q(Q[19:18]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff10 (.CLK(CLK), .EN(1'bx), .SRST(SRST), .D(D), .Q(Q[21:20]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff11 (.CLK(CLK), .EN(1'bx), .SRST(SRST), .D(D), .Q(Q[23:22]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff12 (.CLK(CLK), .EN(1'bx), .SET(SET), .CLR(CLR), .D(D), .Q(Q[25:24]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff13 (.EN(1'bx), .D(D), .Q(Q[27:26]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff14 (.EN(1'bx), .ARST(ARST), .D(D), .Q(Q[29:28]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff15 (.EN(1'bx), .SET(SET), .CLR(CLR), .D(D), .Q(Q[31:30]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-count 2 t:$dffe
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select -assert-count 4 t:$dlatch
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select -assert-count 4 t:$sr
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select -assert-none t:$dffe t:$dlatch t:$sr %% %n t:* %i
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design -load orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 2 t:$dffe
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select -assert-count 1 t:$adffe
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select -assert-count 1 t:$sdffe
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select -assert-count 1 t:$sdffce
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select -assert-count 1 t:$dffsre
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select -assert-count 3 t:$dlatch
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select -assert-count 1 t:$adlatch
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select -assert-count 1 t:$dlatchsr
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select -assert-count 2 t:$sr
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-count 4 t:$_DFFE_??_
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select -assert-count 8 t:$_DLATCH_?_
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select -assert-count 8 t:$_SR_??_
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select -assert-none t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 4 t:$_DFFE_??_
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select -assert-count 2 t:$_DFFE_????_
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select -assert-count 2 t:$_SDFFE_????_
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select -assert-count 2 t:$_SDFFCE_????_
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select -assert-count 2 t:$_DFFSRE_????_
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select -assert-count 6 t:$_DLATCH_?_
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select -assert-count 2 t:$_DLATCH_???_
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select -assert-count 2 t:$_DLATCHSR_???_
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select -assert-count 4 t:$_SR_??_
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