mirror of https://github.com/YosysHQ/yosys.git
50 lines
2.5 KiB
Plaintext
50 lines
2.5 KiB
Plaintext
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### Replace FFs with a const.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input EN;
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(* init=84'haaaaaaaaaaaaaaaaaaaaa *)
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output [83:0] Q;
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input SRST;
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input ARST;
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input [3:0] CLR;
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input [3:0] SET;
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$dff #(.CLK_POLARITY(1'b1), .WIDTH(4)) ff0 (.CLK(CLK), .D(4'hc), .Q(Q[3:0]));
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$dffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .WIDTH(4)) ff1 (.CLK(CLK), .EN(EN), .D(4'hc), .Q(Q[7:4]));
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$adff #(.CLK_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(8'hf0), .WIDTH(8)) ff2 (.CLK(CLK), .ARST(ARST), .D(8'hcc), .Q(Q[15:8]));
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$adffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(8'hf0), .WIDTH(8)) ff3 (.CLK(CLK), .EN(EN), .ARST(ARST), .D(8'hcc), .Q(Q[23:16]));
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$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(8'hf0), .WIDTH(8)) ff4 (.CLK(CLK), .SRST(SRST), .D(8'hcc), .Q(Q[31:24]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(8'hf0), .WIDTH(8)) ff5 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(8'hcc), .Q(Q[39:32]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(8'hf0), .WIDTH(8)) ff6 (.CLK(CLK), .EN(EN), .SRST(SRST), .D(8'hcc), .Q(Q[47:40]));
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$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(8)) ff7 (.CLK(CLK), .SET({SET, 4'hf}), .CLR({4'h0, CLR}), .D(8'hcc), .Q(Q[55:48]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b0), .SET_POLARITY(1'b1), .WIDTH(8)) ff8 (.CLK(CLK), .EN(EN), .SET({SET, 4'h0}), .CLR({4'hf, CLR}), .D(8'hcc), .Q(Q[63:56]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(4)) ff9 (.EN(EN), .D(4'hc), .Q(Q[67:64]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(8'hf0), .WIDTH(8)) ff10 (.EN(EN), .ARST(ARST), .D(8'hcc), .Q(Q[75:68]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(8)) ff11 (.EN(EN), .SET({SET, 4'h0}), .CLR({4'h0, CLR}), .D(8'hcc), .Q(Q[83:76]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$dffe r:WIDTH=2 %i
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select -assert-count 1 t:$adff r:WIDTH=6 %i
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select -assert-count 1 t:$adffe r:WIDTH=6 %i
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select -assert-count 1 t:$sdff r:WIDTH=6 %i
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select -assert-count 1 t:$sdffe r:WIDTH=6 %i
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select -assert-count 1 t:$sdffce r:WIDTH=6 %i
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select -assert-count 1 t:$dffsr r:WIDTH=6 %i
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select -assert-count 1 t:$dffsre r:WIDTH=6 %i
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select -assert-count 1 t:$dlatch r:WIDTH=2 %i
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select -assert-count 1 t:$adlatch r:WIDTH=6 %i
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select -assert-count 1 t:$dlatchsr r:WIDTH=6 %i
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