yosys/techlibs/greenpak4/cells_blackbox.v

19 lines
365 B
Verilog
Raw Permalink Normal View History

2017-08-29 16:17:29 -05:00
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output reg OUT;
output reg[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
parameter COUNT_TO = 1;
parameter RESET_MODE = "RISING";
parameter RESET_TO_MAX = "1";
2017-08-29 16:17:29 -05:00
parameter HAS_POUT = 0;
parameter HAS_CE = 0;
parameter WIDTH = 8;
parameter DIRECTION = "DOWN";
endmodule