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yosys/examples/osu035/example.ys

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Add examples/osu035
2017-05-23 11:38:20 -05:00
read_verilog example.v
read_liberty -lib osu035_stdcells.lib
synth -top top
dfflibmap -liberty osu035_stdcells.lib
Add timing constraints to osu035 example
2017-10-10 06:32:04 -05:00
abc -D 10000 -constr example.constr -liberty osu035_stdcells.lib
Add examples/osu035
2017-05-23 11:38:20 -05:00
opt_clean
stat -liberty osu035_stdcells.lib
write_edif example.edif