2013-09-14 06:29:11 -05:00
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* supply voltages
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.global Vss Vdd
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Vss Vss 0 DC 0
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Vdd Vdd 0 DC 3
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* simple transistor model
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.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
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.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
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* load design and library
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.include cmos_cells.sp
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2016-03-02 05:07:57 -06:00
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.include synth.sp
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2013-09-14 06:29:11 -05:00
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* input signals
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Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
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Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
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Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
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Xuut clk rst en out0 out1 out2 COUNTER
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.tran 0.01 50
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.control
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run
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plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
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.endc
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.end
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